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fsm component test

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Jul 16th, 2019
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  1. // Testbench
  2. module test;
  3.  
  4. reg clk;
  5. reg reset;
  6. reg en;
  7. wire [6:0] out1;
  8.  
  9. // Instantiate device under test
  10. component02 component02(.clk_x2(clk),
  11. .reset(reset),
  12. .en(en),
  13. .phases(out1));
  14.  
  15. initial begin
  16. // Dump waves
  17. $dumpfile("dump.vcd");
  18. $dumpvars(1, test);
  19. en = 1;
  20. clk = 0;
  21. reset = 1;
  22. toggle_clk;
  23.  
  24. reset = 0;
  25. toggle_clk;
  26. toggle_clk;
  27. toggle_clk;
  28. toggle_clk;
  29. toggle_clk;
  30. toggle_clk;
  31. toggle_clk;
  32. toggle_clk;
  33. toggle_clk;
  34. toggle_clk;
  35. toggle_clk;
  36. toggle_clk;
  37. toggle_clk;
  38. toggle_clk;
  39. toggle_clk;
  40. toggle_clk;
  41. toggle_clk;
  42. toggle_clk;
  43. toggle_clk;
  44. toggle_clk;
  45.  
  46.  
  47. end
  48.  
  49. task toggle_clk;
  50. begin
  51. #10 clk = ~clk;
  52. #10 clk = ~clk;
  53. end
  54. endtask
  55.  
  56. endmodule
  57.  
  58. /*******************************************************************************
  59. * Description:
  60. * Verilog implementation autogenerated from component02.cyudb at 07/14/2019 15:31:46.
  61. *
  62. * Note:
  63. * This module definition will automatically be incorporated during the "HDL Generation"
  64. * phase of a design which uses this UDB document.
  65. * Alternatively, the contents of this pane may be copied and used as a starting point
  66. * for a verilog component implementation. The Datapath Configuration Tool may be used
  67. * to adjust advanced datapath parameters (accessible from the Tools menu).
  68. * For more details, see the Component Author Guide and Technical Reference Manuals.
  69. * Both can be accessed by selecting Help -> Documentation.
  70. *******************************************************************************/
  71.  
  72. //`include "cypress.v"
  73. /* ==================== Include Component Definitions ==================== */
  74.  
  75. module component02 (
  76. input wire clk_x2, /* 200khz clock */
  77. input wire reset,
  78. input wire en,
  79. output reg [6:0] phases
  80. );
  81. /* b6= p6 ... b0 = p0, p0 = clk */
  82. //localparam START = 7'b0;
  83. localparam STATE_0 = 7'b0001000;
  84. localparam STATE_1 = 7'b1000001;
  85. localparam STATE_2 = 7'b0000000;
  86. localparam STATE_3 = 7'b0000011;
  87. localparam STATE_4 = 7'b0000110;
  88. localparam STATE_5 = 7'b0000101;
  89. localparam STATE_6 = 7'b0100000;
  90. localparam STATE_7 = 7'b0011001;
  91.  
  92. integer count = 0;
  93. always @(posedge clk_x2)
  94. begin
  95. $display("@%8b count %d",phases, count);
  96. if (reset)
  97. begin
  98. count <= 0;
  99. phases <= STATE_0;
  100. end
  101. else
  102. if (en)
  103. begin
  104. if (count >= 7)
  105. begin
  106. count <= 0;
  107. end
  108. else
  109. begin
  110. count <= count + 1;
  111. end
  112. case (count)
  113. 0:
  114. begin
  115. phases <= STATE_1;
  116. end
  117. 1:
  118. begin
  119. phases <= STATE_2;
  120. end
  121. 2:
  122. begin
  123. phases <= STATE_3;
  124. end
  125. 3:
  126. begin
  127. phases <= STATE_4;
  128. end
  129. 4:
  130. begin
  131. phases <= STATE_5;
  132. end
  133. 5:
  134. begin
  135. phases <= STATE_6;
  136. end
  137. 6:
  138. begin
  139. phases <= STATE_7;
  140. end
  141. 7:
  142. begin
  143. phases <= STATE_0;
  144. end
  145. default:
  146. begin
  147. phases <= STATE_0;
  148. end
  149. endcase
  150. end
  151. end
  152.  
  153. endmodule
  154.  
  155. Log:
  156. VSIMSA: Configuration file changed: `/home/runner/library.cfg'
  157. ALIB: Library `work' attached.
  158. work = /home/runner/work/work.lib
  159. MESSAGE "Pass 1. Scanning modules hierarchy."
  160. MESSAGE "Pass 2. Processing instantiations."
  161. MESSAGE "Pass 3. Processing behavioral statements."
  162. MESSAGE "Running Optimizer."
  163. MESSAGE "ELB/DAG code generating."
  164. MESSAGE "Unit top modules: test."
  165. MESSAGE "$root top modules: test."
  166. SUCCESS "Compile success 0 Errors 0 Warnings Analysis time: 0[s]."
  167. ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
  168. done
  169. # Aldec, Inc. Riviera-PRO version 2014.10.81.5580 built for Linux64 on October 24, 2014.
  170. # HDL, SystemC, and Assertions simulator, debugger, and design environment.
  171. # (c) 1999-2014 Aldec, Inc. All rights reserved.
  172. vsim +access+r;
  173. # ELBREAD: Elaboration process.
  174. # ELBREAD: Elaboration time 0.0 [s].
  175. # KERNEL: Main thread initiated.
  176. # KERNEL: Kernel process initialization phase.
  177. # KERNEL: Time resolution set to 1ns.
  178. # ELAB2: Elaboration final pass...
  179. # KERNEL: PLI/VHPI kernel's engine initialization done.
  180. # PLI: Loading library '/usr/share/riviera-pro-2014.10-x86_64/bin/libsystf.so'
  181. # ELAB2: Create instances ...
  182. # ELAB2: Create instances complete.
  183. # SLP: Started
  184. # SLP: Elaboration phase ...
  185. # SLP: Elaboration phase ... done : 0.0 [s]
  186. # SLP: Generation phase ...
  187. # SLP: Generation phase ... done : 0.1 [s]
  188. # SLP: Finished : 0.1 [s]
  189. # SLP: 0 primitives and 2 (100.00%) other processes in SLP
  190. # SLP: 9 (100.00%) signals in SLP and 0 interface signals
  191. # ELAB2: Elaboration final pass complete - time: 0.1 [s].
  192. # KERNEL: SLP loading done - time: 0.0 [s].
  193. # KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
  194. # KERNEL: Warning: Contact Aldec for available upgrade options - [email protected].
  195. # KERNEL: SLP simulation initialization done - time: 0.0 [s].
  196. # KERNEL: Kernel process initialization done.
  197. # Allocation: Simulator allocated 5284 kB (elbread=1023 elab2=4110 kernel=150 sdf=0)
  198. # KERNEL: ASDB file was created in location /home/runner/dataset.asdb
  199. run -all;
  200. # KERNEL: @ xxxxxxx count 0
  201. # KERNEL: @ 0001000 count 0
  202. # KERNEL: @ 1000001 count 1
  203. # KERNEL: @ 0000000 count 2
  204. # KERNEL: @ 0000011 count 3
  205. # KERNEL: @ 0000110 count 4
  206. # KERNEL: @ 0000101 count 5
  207. # KERNEL: @ 0100000 count 6
  208. # KERNEL: @ 0011001 count 7
  209. # KERNEL: @ 0001000 count 0
  210. # KERNEL: @ 1000001 count 1
  211. # KERNEL: @ 0000000 count 2
  212. # KERNEL: @ 0000011 count 3
  213. # KERNEL: @ 0000110 count 4
  214. # KERNEL: @ 0000101 count 5
  215. # KERNEL: @ 0100000 count 6
  216. # KERNEL: @ 0011001 count 7
  217. # KERNEL: @ 0001000 count 0
  218. # KERNEL: @ 1000001 count 1
  219. # KERNEL: @ 0000000 count 2
  220. # KERNEL: @ 0000011 count 3
  221. # KERNEL: Simulation has finished. There are no more test vectors to simulate.
  222. exit
  223. # VSIM: Simulation has finished.
  224. Done
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