fsm component test

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Jul 16th, 2019

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// Testbench
module test;
reg clk;
reg reset;
reg en;
wire [6:0] out1;
// Instantiate device under test
component02 component02(.clk_x2(clk),
.reset(reset),
.en(en),
.phases(out1));
initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1, test);
en = 1;
clk = 0;
reset = 1;
toggle_clk;
reset = 0;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
toggle_clk;
end
task toggle_clk;
begin
#10 clk = ~clk;
#10 clk = ~clk;
end
endtask
endmodule
/*******************************************************************************
* Description:
* Verilog implementation autogenerated from component02.cyudb at 07/14/2019 15:31:46.
*
* Note:
* This module definition will automatically be incorporated during the "HDL Generation"
* phase of a design which uses this UDB document.
* Alternatively, the contents of this pane may be copied and used as a starting point
* for a verilog component implementation. The Datapath Configuration Tool may be used
* to adjust advanced datapath parameters (accessible from the Tools menu).
* For more details, see the Component Author Guide and Technical Reference Manuals.
* Both can be accessed by selecting Help -> Documentation.
*******************************************************************************/
//`include "cypress.v"
/* ==================== Include Component Definitions ==================== */
module component02 (
input wire clk_x2, /* 200khz clock */
input wire reset,
input wire en,
output reg [6:0] phases
);
/* b6= p6 ... b0 = p0, p0 = clk */
//localparam START = 7'b0;
localparam STATE_0 = 7'b0001000;
localparam STATE_1 = 7'b1000001;
localparam STATE_2 = 7'b0000000;
localparam STATE_3 = 7'b0000011;
localparam STATE_4 = 7'b0000110;
localparam STATE_5 = 7'b0000101;
localparam STATE_6 = 7'b0100000;
localparam STATE_7 = 7'b0011001;
integer count = 0;
always @(posedge clk_x2)
begin
$display("@%8b count %d",phases, count);
if (reset)
begin
count <= 0;
phases <= STATE_0;
end
else
if (en)
begin
if (count >= 7)
begin
count <= 0;
end
else
begin
count <= count + 1;
end
case (count)
0:
begin
phases <= STATE_1;
end
1:
begin
phases <= STATE_2;
end
2:
begin
phases <= STATE_3;
end
3:
begin
phases <= STATE_4;
end
4:
begin
phases <= STATE_5;
end
5:
begin
phases <= STATE_6;
end
6:
begin
phases <= STATE_7;
end
7:
begin
phases <= STATE_0;
end
default:
begin
phases <= STATE_0;
end
endcase
end
end
endmodule
Log:
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE "Pass 2. Processing instantiations."
MESSAGE "Pass 3. Processing behavioral statements."
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: test."
MESSAGE "$root top modules: test."
SUCCESS "Compile success 0 Errors 0 Warnings Analysis time: 0[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
done
# Aldec, Inc. Riviera-PRO version 2014.10.81.5580 built for Linux64 on October 24, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
vsim +access+r;
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ns.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library '/usr/share/riviera-pro-2014.10-x86_64/bin/libsystf.so'
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# SLP: Started
# SLP: Elaboration phase ...
# SLP: Elaboration phase ... done : 0.0 [s]
# SLP: Generation phase ...
# SLP: Generation phase ... done : 0.1 [s]
# SLP: Finished : 0.1 [s]
# SLP: 0 primitives and 2 (100.00%) other processes in SLP
# SLP: 9 (100.00%) signals in SLP and 0 interface signals
# ELAB2: Elaboration final pass complete - time: 0.1 [s].
# KERNEL: SLP loading done - time: 0.0 [s].
# KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
# KERNEL: Warning: Contact Aldec for available upgrade options - [email protected].
# KERNEL: SLP simulation initialization done - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 5284 kB (elbread=1023 elab2=4110 kernel=150 sdf=0)
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
# KERNEL: @ xxxxxxx count 0
# KERNEL: @ 0001000 count 0
# KERNEL: @ 1000001 count 1
# KERNEL: @ 0000000 count 2
# KERNEL: @ 0000011 count 3
# KERNEL: @ 0000110 count 4
# KERNEL: @ 0000101 count 5
# KERNEL: @ 0100000 count 6
# KERNEL: @ 0011001 count 7
# KERNEL: @ 0001000 count 0
# KERNEL: @ 1000001 count 1
# KERNEL: @ 0000000 count 2
# KERNEL: @ 0000011 count 3
# KERNEL: @ 0000110 count 4
# KERNEL: @ 0000101 count 5
# KERNEL: @ 0100000 count 6
# KERNEL: @ 0011001 count 7
# KERNEL: @ 0001000 count 0
# KERNEL: @ 1000001 count 1
# KERNEL: @ 0000000 count 2
# KERNEL: @ 0000011 count 3
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit
# VSIM: Simulation has finished.
Done

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